In known wafer level packaging (WLP) processes, a carrier wafer may be laminated to dicing tape and known good die are placed face down. The wafer may then be compression molded to encapsulate it and then the wafer carrier and tape may be removed. The molding compound may then be used to carry the fan-out area and to protect the chip backside. Redistribution layers may be created on the exposed die faces, the I/O may be rerouted, solder balls may be placed, and the die may be singulated. In other conventional non wafer level processes, methods include slicing the wafer into individual die and then packaging them.
Few semiconductor packaging and assembly techniques currently utilize embedded conductive circuits. When utilized, most embedded circuit implementations include a conductive circuit layer that is patterned onto a surface of a metal core base layer. A dielectric material is then layered onto the conductive circuit followed by the application of a thin layer of conductive layer. This foil is then etched to complete the circuit.
However, there are various limitations inherent in these known processes. Therefore, improved layering structures for semiconductor devices would be well received in the art.